1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device and a method of forming the semiconductor device, and particularly to a semiconductor device aimed at preventing short-circuiting of a semiconductor substrate and a contact plug in a peripheral circuit region of a vertical transistor in the semiconductor device containing the vertical transistor, and a method of forming the semiconductor device.
2. Description of Related Art
In recent years, high integration of semiconductor devices, such as DRAM (dynamic random access memory), has been taking place rapidly. A MOS (metal-oxide semiconductor) transistor that is integrated on a semiconductor device is required to be formed in such a way as to have a smaller surface area. As a MOS transistor that can be formed in high density on the semiconductor substrate, a vertical MOS transistor (pillar transistor) is available. The vertical MOS transistor is a transistor whose gate electrode is formed on a side wall of a columnar semiconductor (pillar semiconductor).
More specifically, in the vertical MOS transistor, a gate electrode of a transistor and an embedded bit line are formed in such a way as to encircle a pillar, which is made by processing an upper portion of the semiconductor substrate and to be at different heights and cross each other at substantially right angles. The gate electrode is a wire that functions as an embedded word line, and extends in one direction (X-direction in this case) and above the embedded bit line. Each embedded bit line extends in a Y-direction that is at a certain angle to the X-direction. Between the pillars that are arranged in the X-direction, embedded bit lines that extend in the Y-direction are formed. Each embedded bit line is shared by a plurality of pillars that are arranged in the Y-direction.
If the semiconductor device is applied to DRAM, a pair of embedded word lines (gate electrodes) may work as a double gate connected to one pillar. In such a case, the embedded bit line is connected only to a one-side pillar. A bottom surface of the embedded bit line is connected to a protective film such as insulator.
The bottom surface of the embedded bit line is insulated from the semiconductor substrate by an insulating film, which is formed on a bottom surface of a groove of the semiconductor substrate. A side surface of the embedded bit line is insulated by a bit insulating film, which is formed on an inner side wall of the groove, and is not connected to a pillar that is on the opposite side of a pillar that is to be connected. Moreover, the embedded bit line is connected to a lower diffusion region via a contact plug (bit contact), which is provided in such a way as to pass through a side surface of an insulating film near a pillar which the embedded bit line is in contact with. Incidentally, without the use of the bit contact, the embedded bit line and the lower diffusion region may be disposed so as to be in direct contact with each other.
In many cases, the semiconductor substrate used for such a semiconductor device is made of p-type silicon. Below a groove of the semiconductor substrate that is formed at the time of making pillars, a diffusion region to which n-type impurities have been added may be formed. This lower diffusion region constitutes a source-drain region of a vertical MOS transistor.
Moreover, above each pillar, an upper diffusion region is formed. The upper diffusion region constitutes a source-drain region of the vertical MOS transistor; impurities have been added to the upper diffusion region, as in the case of the lower diffusion region. On the upper diffusion region, an upper wire of the semiconductor device is provided.
If the semiconductor device is applied to DRAM, on the upper diffusion region, a capacitor (capacitance) is formed via a contact plug (capacitor contact). In many cases, a cylinder-type capacitor that includes a lower electrode, a capacitance insulating film, and an upper electrode is used. The pillars and capacitor contacts each are separated by an interlayer insulating film. Incidentally, without the use of the capacitor contacts, the upper diffusion region and the capacitor or upper wire may be disposed on the upper diffusion region in such a way as to be in direct contact with the upper diffusion region.
As described above, it is clear that one vertical MOS transistor is made up of a lower diffusion region and an upper diffusion region, which function as source-drain regions, a pillar portion, which is between the above regions and is a part of a semiconductor substrate, and a pair of gate electrodes, which are formed so as to face both side walls of the pillar portion.
In Japanese Patent Application Laid-open No. 2011-155064, related technology of the vertical MOS transistor having the above configuration is disclosed. More specifically, Japanese Patent Application Laid-open No. 2011-155064 discloses a technique which makes it possible to reduce the wiring capacitance of the memory cell region and to reduce the wiring resistance in the peripheral circuit region by forming, in a peripheral circuit region having a planar MOS transistor, a periphery upper wire that is thicker than a cell upper wire of a memory cell region having the vertical MOS transistor.
In this kind of vertical MOS transistor, as described above, the gate electrode that serves as the word line, and the bit line are embedded in the semiconductor substrate. Therefore, a contact plug (referred to as a power-supply contact plug, hereinafter) for supplying power to the embedded bit line and the embedded word line need to be formed deeper than those of a planar transistor. If a vertical MOS transistor is used in a memory cell region as in the case of DRAM, parts of the embedded bit line and embedded word line (contact portions) are formed so as to extend in a peripheral region, and the power-supply contact plug is formed in each of the contact portions.
Moreover, in order to prevent an increase in the number of forming steps of the semiconductor device containing the vertical MOS transistors, the power-supply contact plugs for the embedded bit lines and embedded word lines are preferably formed at once by etching or the like. However, because of the above-described relative positional relationship between the embedded bit lines and the embedded word lines, the contact plugs for the embedded bit lines will be different in depth from the contact plugs for the embedded word lines. Therefore, it is important to secure a margin when etching of the power-supply contact plugs and substrate is performed. With the above fact taken into account, in order to prevent short-circuiting of the contact plugs and the semiconductor substrate, a contact portion of the embedded word line and a contact hole in which the power-supply contact plug thereof is formed is actually formed inside an insulating film such as STI (shallow trench isolation).
However, in a process of forming, at once, contact plugs for supplying power to the embedded bit lines and the embedded word lines, because the embedded word lines are formed at a shallower position compared with the embedded bit lines before the process as described above, if etching of a contact hole in which a bit line contact plug is to be formed is performed at a proper depth, that etching could be excessive for a contact hole in which a word line contact plug is to be formed.
The word line contact hole may be formed in the insulating film of STI or the like of a peripheral circuit region in the same way as before. However, the depth of the STI is not enough relative to the depth of the embedded bit lines. Meanwhile, it is not easy to form a deep STI in terms of embedding. Therefore, the problem is that the semiconductor substrate and contact plugs in the semiconductor device might be short-circuited due to lack of a sufficient short margin between a word line contact plug and the semiconductor substrate.